The present invention relates to a method and apparatus for Architectural Level Power-Aware Optimization and Risk Mitigation.
The distribution of power is often as important as the level of power consumed in a product. Even with a lower level of power consumed, if the consumers are located in a confined area, this may cause significant voltage drop at this location. This subsequently causes the degradation in performance at that location. This is referred as a Voltage Drop/IR Hot Spot.
Typically, an architect develops an architecture from algorithm and/or product specification by partitioning the product into hardware and software. Then, designers translate the architecture into an intermediate code such as register transfer language (RTL) code. Floor planning is then done, and then an IC layout can be generated. After layout, a hot spot analysis can be done for the layout and if the hot-spot analysis indicates that IR hot spots arising from the current design are unacceptable, the user can restart the entire sequence of architecture, RTL, floor planning, layout and hot spot analysis. This process can be very lengthy and can cost millions of dollars depending on the complexity of the design.